By John G. Webster (Editor)
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Additional info for 64.VLSI Systems
Pipelining after each 1 bit addition, the multiplier architecture is very similar to that described in Ref. 143. The clock signals are distributed in metal outside the multiplier array and in polycide (strapped polysilicon with silicide to minimize the line resistance) inside the multiplier array. Two-phase clocking is used with a total master and slave register fanout of 8 pF. No special circuitry to prevent overlap of the two-phase clock is used because this degrades the active-high portion of the clock signal.
Minimize TCP subject to the local and global timing constraints: TSkew ≤ TCP − TPD(max) = TCP − (TC-Q + TLogic(max) + TInt + TSet-up ) for TCi > TC f |TSkew | ≤ TPD(min) = TC-Q + TLogic(min) + TInt + THold Minimize TCP subject to R1 − R2 : R2 − R2 : R3 − R4 : R3 − R2 : R1 − R4 : C1 − C2 = TSkew12 ≥ −20 ns TSkew12 − TCP ≤ −22 ns C2 − C3 = TSkew23 ≥ −26 ns TSkew23 − TCP ≤ −27 ns C3 − C4 = TSkew34 ≥ −2 ns TSkew34 − TCP ≤ −3 ns C3 − C2 = TSkew32 ≥ −2 ns TSkew32 − TCP ≤ −3 ns TSkew12 + TSkew23 + TSkew34 = 0 where the optimal clock schedule is TSkew12 = −3 ns TSkew23 = −12 ns TSkew34 = 15 ns TCP = 19 ns If zero clock skew between off-chip registers is not considered, the minimum clock period is TCP ϭ 15 ns.
Thus, decreasing the resistance at the source by increasing the line width affects the total path delay more significantly than decreasing the resistance at the leaf node because more capacitance is seen by the large source resistance than if the resistance is greater near the leaf. Therefore, the clock skew is particularly sensitive to changes in line width close to the clock source. One approach to making the clock lines more tolerant of process variations is to make the width of the clock interconnect lines widest near the clock source and thinner as the leaf nodes are approached.
64.VLSI Systems by John G. Webster (Editor)